SpiSlave.h

Go to the documentation of this file.

#ifndef _SPISLAVE_H
#define _SPISLAVE_H
#include <stdint.h>
#include <stdbool.h>
#include "ReadWriteBits.h"
#include "Spi.h"
 
#ifdef USE_FAKES
#include "Spi_faked.h"
#include "SpiSlave_faked.h" // declare fakes
#endif
 
// ---Private---
inline void _SignalDataReady(void)
{
    ClearBit(Spi_PortOutput, Spi_DataReady);
    // ---Expected Assembly---
    //  cbi 0x05, 1 ; 5
}
inline void _SignalDataNotReady(void)
{
    SetBit(Spi_PortOutput, Spi_DataReady);
    // ---Expected Assembly---
    //  sbi 0x05, 1 ; 5
}
 
// ---API (Go to the Doxygen documentation of this file)---
inline void DisableSpiInterrupt(void)
{
 
    // Disable the "transfer complete" interrupt
    ClearBit(Spi_SPCR, Spi_InterruptEnable);
    // ---Expected Assembly---
    // in   r24, 0x2c   ; 44
    // andi r24, 0x7F   ; 127
    // out  0x2c, r24   ; 44
    // This is three instructions because SPCR is outside the
    // address range for using `cbi`.
}
 
// ---API functions that call fakes when testing---
//
#ifdef USE_FAKES
#define ClearSpiInterruptFlag ClearSpiInterruptFlag_fake
#endif
inline void EnableSpiInterrupt(void)
{
    // Global interrupt disable
    cli(); // cli
    // Clear SPI interrupt flag (SPIF) before enabling interrupt
    ClearSpiInterruptFlag();
    // Enable the "transfer complete" interrupt
    SetBit(Spi_SPCR, Spi_InterruptEnable);
    // ---Expected Assembly---
    // in r24, 0x2c; 
    // ori r24, 0x80;
    // out 0x2c, r24
    // This is three instructions because SPCR is outside the
    // address range for using `sbi`.
    //
    // Global interrupt enable
    sei(); // sei
}
#ifdef USE_FAKES
#undef ClearSpiInterruptFlag
#endif
 
#ifdef USE_FAKES
// Call fakes by renaming faked calls with _fake suffix.
#define EnableSpiInterrupt EnableSpiInterrupt_fake
#endif
inline void SpiSlaveInit(void)
{
    // DataReady pin idle high
    SetBit(Spi_PortOutput, Spi_DataReady); // sbi   0x05, 1
    // Set DataReady as an output pin
    SetBit(Spi_PortDirection, Spi_DataReady); // sbi    0x04, 1
 
    // Set Miso as an an output pin
    SetBit(Spi_PortDirection, Spi_Miso); // sbi 0x04, 4
 
    _EnableSpiModule();
    // Enable interrupts for robust SPI communication
    EnableSpiInterrupt();
}
#ifdef USE_FAKES
// Remove `_fake` suffix from function names.
#undef EnableSpiInterrupt
#endif
 
#ifdef USE_FAKES
#define _SpiTransferIsDone _SpiTransferIsDone_fake
#define _SignalDataReady _SignalDataReady_fake
#define DisableSpiInterrupt DisableSpiInterrupt_fake
#endif
inline void SpiSlaveTxByte(uint8_t input_byte)
{
 
    *Spi_SPDR = input_byte;
    // ---Expected Assembly---
    // out  0x2e, r23   ; 46
    DisableSpiInterrupt();
    // ---Expected Assembly---
    // in   r24, 0x2c   ; 44
    // andi r24, 0x7F   ; 127
    // out  0x2c, r24   ; 44
    _SignalDataReady();
    // ---Expected Assembly---
    // cbi  0x05, 1 ; 5
    // Wait for a byte from the SPI Master.
    while ( !_SpiTransferIsDone() ); // Check SPI interrupt flag
    // ---Expected Assembly---
    // Total number of cycles: 5
    // in   r0, 0x2d
    // sbrs r0, 7
    // rjmp .-6
    _SignalDataNotReady();
    // Re-enable interrupt and reset (clear) SPI interrupt flag
    EnableSpiInterrupt();
    // ---Expected Assembly---
    // Total number of cycles: 7
    // cli
    // in   r24, 0x2d
    // in   r24, 0x2e
    // in   r24, 0x2c
    // ori  r24, 0x80
    // out  0x2c, r24
    // sei
}
#ifdef USE_FAKES
#undef _SpiTransferIsDone
#undef _SignalDataReady
#undef DisableSpiInterrupt
#endif
 
#ifdef USE_FAKES
#define SpiSlaveTxByte SpiSlaveTxByte_fake
#endif
inline void SpiSlaveTx(uint8_t const *input_buffer, uint16_t nbytes)
{
    uint16_t byte_index;
    for (byte_index = 0; byte_index < nbytes; byte_index++)
    {
        SpiSlaveTxByte(input_buffer[byte_index]);
    }
}
#ifdef USE_FAKES
#undef SpiSlaveTxByte
#endif
 
#endif // _SPISLAVE_H